HORIZON将硬件设计转化为仓库级代码进化，AI智能体框架实现硬件自进化，颠覆传统设计流程。
arXiv:2606.28279v1 Announce Type: cross Abstract: We present HORIZON, a self-evolving agent framework that treats hardware design as repository-level …
利用LLM自动定位和修复Verilog代码错误，开创硬件调试新范式
arXiv:2606.23759v1 Announce Type: cross Abstract: Verilog debugging remains one of the most time-consuming stages in digital circuit design. Recent ad…
研究大语言模型在硬件RTL编码中的失败与泛化表现，揭示AI辅助硬件设计的边界与潜力。
arXiv:2606.19347v1 Announce Type: cross Abstract: Translating sequential programming priors into the parallel temporal logic of hardware design remain…
用LLM自动重写RTL代码实现时钟门控，AI+硬件设计前沿研究。
arXiv:2606.17461v1 Announce Type: cross Abstract: Fine-grain clock gating (FGCG) is among the most effective techniques for reducing dynamic power, ye…
LLM借助工具辅助生成RTL代码，硬件设计效率有望革新。
arXiv:2606.15500v1 Announce Type: cross Abstract: Large language models (LLMs) have facilitated impressive progress in software engineering, code gene…
基于功能估计引导，自动生成高质量RTL代码，加速硬件设计流程。
arXiv:2606.09867v1 Announce Type: cross Abstract: Optimizing register transfer level (RTL) code is of vital importance in hardware design. Large langu…
逐步过程奖励引导LLM微调，提升RTL合成质量的创新方法
arXiv:2606.04246v1 Announce Type: new Abstract: Automatic generation of RTL code for digital hardware designs remains challenging due to long-horizon …
用自然语言描述电路需求，AI自动生成PCB原理图，开启硬件设计新范式
arXiv:2606.01188v1 Announce Type: cross Abstract: Translating natural-language hardware requirements into correct printed circuit board (PCB) schemati…
用LLM智能体代替繁琐的手动调参，自动优化模拟与混合信号电路尺寸，芯片设计效率大提升！
arXiv:2602.02849v2 Announce Type: replace Abstract: The design of Analog and Mixed-Signal (AMS) integrated circuits remains heavily reliant on expert …
用自然语言描述就能自动生成电路原理图，多智能体LLM框架为硬件设计带来新可能
arXiv:2601.04505v3 Announce Type: replace Abstract: Generating accurate circuit schematics from high-level natural language descriptions remains a per…