Benchmarking LLMs for Verilog Design Flows
评估主流大模型在Verilog设计流程中的表现,提供首个系统对比基准,对硬件设计自动化与芯片开发有重要参考价值
arXiv:2607.22759v1 Announce Type: cross Abstract: Large language models (LLMs) show promise in code generation, but their capabilities to produce corr…