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HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification
为LLM驱动的层次化硬件形式验证，提出数据合成管道、数据集与基准，填补硬件安全验证缺口。
arXiv:2606.13706v1 Announce Type: cross Abstract: We present HierSVA, an integrated suite that combines a pipeline, dataset, and benchmark for LLM-dri…